1. Technical Field of the Invention
The present invention relates to writing data into a memory and, in particular, to controlling the generation of a self-timed write reset pulse which instructs the memory to reset itself in preparation for a next write operation.
2. Description of Related Art
Reference is now made to FIG. 1 wherein there is shown a circuit diagram of a prior art memory cell 10 suitable for placement within a memory array (not shown). The memory cell 10 as illustrated comprises a four transistor static memory cell such as that commonly used in a static random access memory (SRAM) type of memory array. The memory cell 10 includes two gate/drain cross-coupled transistors 12 and 14, along with two access transistors 16 and 18. A first bit line (bit line true--BLT) 20 is connected to one of the access transistors 16. A second bit line (bit line complement--BVC) 22 is connected to the other of the access transistors 18. At nodes 30 and 32, the drains 12d and 14d of the cross-coupled transistors 12 and 14 are connected to their respective access transistors 16 and 18, and are also connected to a voltage supply (Vcc) through a pair of poly resistors 24 and 26, respectively. The gates 16g and 18g of the access transistors 16 and 18 are connected to a word line (WL) 28. Data is stored by the memory cell 10 at the nodes 30 and 32 (with the data at node 30 being the true data, and the data at node 32 being the complement data). During a read or write operation, bit line 20 and 22 access to the nodes 30 and 32, respectively, is provided by driving the word line 28 high, and thus turning on the access transistors 16 and 18.
Reference is now made to FIG. 2 wherein there is shown a block diagram of a portion of a prior art memory 50. The memory 50 includes a plurality of a memory cells 10 (only one shown for simplification) arranged in an array configuration. A write driver 52 circuit is connected to the bit lines 20 and 22 of the memory cell 10 through a pair of pass transistors 54 and 56 as well as fuses 96. More particularly, a first write bit line (write bit true--WBT) 58 output from the write driver is connected through pass transistor 54 to the bit line true 20. A second write bit line (write bit complement--WBC) 60 is connected through pass transistor 56 to the bit line complement 22. A column select line (COL) 62 is connected to the gates of the pass transistors 54 and 56 and is driven high when selecting the column comprising bit line true 20 and bit line complement 22 for connection to the write bit lines 58 and 60. During the write operation, write driver 52 access to the bit lines 20 and 22 is provided by driving the column select line 62 high. This action turns on the pass transistors 54 and 56 and gives the write driver access to the memory cell 10.
A reset circuit 64 receives the write bit true line 58 and write bit complement line 60 data output from the write driver 52 with each write operation. The reset circuit 64 senses a start of the write operation from detected logic level transitions on either the write bit true line 58 or the write bit complement line 60 at the start of a write operation. The reset circuit 64 then waits for a predetermined amount of time sufficient to allow for completion of the writing of data into the memory cell 10. At that point in time, a reset signal (RESET) 66 pulse is generated. This reset signal 66 is applied to a number of circuits (not shown) within the memory 50 associated with addressing and accessing the memory cell 10. Upon receipt of the reset signal 66, addressing and accessing operations are immediately terminated. Receipt of the reset signal 66 further causes these circuits to reset themselves in preparation for the start of a next write operation.
Reference is now made to FIG. 3 wherein there is shown a circuit diagram for a prior art reset circuit 64. The reset circuit 64 includes a write sensing circuit 68 that operates to detect logic level transitions on the write bit true line 58 and write bit complement line 60 at the start of a write operation. Responsive thereto, write simulation logic 70 simulates the writing of data into the memory cell 10 by flipping the stored data state of a dummy memory cell 10'. A write complete signal in then output from the write simulation logic following completion of the dummy memory write operation. A delay circuit 72 delays passage of the write complete signal for a period of time sufficient to ensure that the write operation has been completed, and then generates the reset signal 66 for output from the reset circuit 64.
The write sensing circuit 68 comprises a NAND gate 74 that receives write bit true line 58 and write bit complement line 60 data output from the write driver 52 at its input. The write simulation logic 70 includes a dummy memory cell 10' comprising a pair of gate/drain cross-coupled memory transistors 12' and 14' and a pair of gate/drain cross-coupled transistors 76 and 78 functioning as an access transistor 16' for the memory cell. The write simulation logic 70 also receives write bit true line 58 and write bit complement line 60 data output from the write driver 52 as inputs. More specifically, the write bit true line 58 is connected to the drain of transistor 76 and to the gate of transistor 78. The write bit complement line 60, on the other hand, is connected to the drain of transistor 78 and to the gate of transistor 76. The sources of transistors 76 and 78 are connected together at node 80. The write simulation logic 70 still further includes a p-channel pull-up transistor 82 and an access transistor 18'. The output of the NAND gate 74 for the write sensing circuit 68 is connected to the gate of pullup transistor 82 and to the source of access transistor 18'. Node 80 is connected to the drain of pull-up transistor 82 and also to the drain of transistor 12' and the gate of transistor 14'. The drain of access transistor 18' at node 84 is connected to the drain of transistor 14' and the gate of transistor 12'. The write simulation logic further comprises a pair of stacked transistors 86 and 88 which are source/drain connected at node 90 to the delay circuit 72. In this configuration, an upper one 86 of the stacked transistors comprises a p-channel device, and a lower one 88 of the stacked transistors comprises an n-channel device. The output of the NAND gate 74 is further connected to the gate of an upper one 86 of the stacked transistors. Node 84 from the dummy memory cell 10' is connected to the gate of a lower one 88 of the stacked transistors.
The cross-coupled transistors 76 and 78 forming the access transistor 16' of the dummy memory cell 10' are sized to replicate and designed to simulate operation of the access transistor 16 for the memory cell 10 of FIG. 1. The access transistor 18' of the dummy memory cell 10' is sized to replicate and designed to simulate operation of the access transistor 18 for the memory cell 10 of FIG. 1. Furthermore, the cross-coupled transistors 12' and 14' of the dummy memory cell 10' are sized to replicate and designed to simulate operation of cross coupled transistors 12 and 14 for the memory cell 10 of FIG. 1. All interconnections between the various circuit components of the dummy memory cell 10' are identical to that presented with the memory cell 10. Thus, although operational characteristics of memory devices may vary from lot to lot, because the memory cell 10 and the dummy memory cell 10' are manufactured on the same die using the same mask exposure and process, the memory cell and dummy memory cell exhibit virtually identical timing and operational performance characteristics. As will be discussed in more detail below, this feature is advantageously utilized in connection with the timely generation of the reset signal 66.
Reference is now made in combination to FIGS. 2 and 3. In preparation for writing data into the memory cell 10, the write bit true line 58 and the write bit complement line 60 are both at logic level high, thus driving the output of the NAND gate 74 to a normally logic level low. This turns on p-channel pull-up transistor 82 to drive node 80 of the dummy memory cell 10' high. This normally logic level low output of NAND gate 74 is further passed through access transistor 18' to node 84, with node 84 also being driven to logic level low due to the turning on of transistor 14'. The high and low, respectively, logic levels of nodes 80 and 84 remain the same at all times during circuit operation except when the write operation itself is being performed.
The output of NAND gate 74 remains at normally logic level low for so long as the write bit true line 58 and write bit complement line 60 both maintain a logic level high indicative of an operational state wherein data is not being written into the memory. Thus, a logic level low output from the NAND gate 74 is applied to the gate of upper stacked p-channel transistor 86, and a logic level low output from node 84 is applied to the gate of the lower stacked transistor 88. This combined logic level low signal application turns on transistor 86 and turns off transistor 88 producing a logic level high output at node 90 which is passed through the delay circuit 72 and output (following an inversion) as the reset signal 66 (at logic level low).
When a write operation is being performed, the write driver 52 receives the data to be written into the memory. Previous to that, the address for the individual memory cell 10 within the memory has been presented and that cell has been selected. The true and complement values of the data to be written are then output on the write bit true line 58 and write bit complement line 60, respectively, and are presented to bit line true and bit line complement 20 and 22, respectively, through the column selected 62 transistors 54 and 56, respectively. Simultaneously, the true and complement values of the data to be written are presented to the NAND gate 74 of the write sensing circuit 68. At this point, one of the write bit lines 58 or 60 goes to a logic level low causing the output of the NAND gate 74 to switch to a logic level high. The occurrence of a write operation is accordingly detected by the write sensing circuit 68, and a signal indicative of this write operation is output from the NAND gate 74 to the write simulation logic 70.
When the NAND gate 74 output goes to logic level high, pull-up transistor 82 of the write simulation logic 70 is turned off. At the same time, one of the access transistor 16' related cross-coupled transistors 76 or 78 is turned off because the corresponding write bit line 58 or 60 connected to its gate has made a transition to logic level low. The remaining one of the cross-coupled transistors 78 or 76 remains on to pass the logic level low signal on one of the low going write bit lines 58 or 60 through to node 80. When this low going signal is applied to the gate of transistor 14', it turns off and node 84 is no longer connected to ground (Vss). With the output of the NAND gate 74 going to logic level high, a logic level high signal is passed through access transistor 18' to node 84, thus driving it also to logic level high. Taking node 84 to a logic level high causes transistor 12' to turn on and pull node 80 to ground (if this has not yet already occurred from the operation of the access transistor 16'). This results in a flipping of the dummy memory cell 10' stored data at nodes 80 and 84 and thus simulate the occurrence of the actual write operation which is simultaneously occurring in the memory cell 10. A logic level high output from the NAND gate 74 is further applied to the gate of upper stacked p-channel transistor 86, and a logic level high output from node 84 of the dummy memory cell 10' is applied to the gate of the lower stacked transistor 88. These simultaneous logic level high signal applications turn off transistor 86 and turn on transistor 88 producing a logic level low output at node 90 (the write complete signal) which is passed through the inverting delay circuit 72 and output as the reset signal 66 pulse (at logic level high). Responsive to the logic level high pulsing of the reset signal 66, operations of the addressing and accessing circuits (not shown) within the memory are immediately terminated. These addressing and accessing circuits are further reset by the pulsed signal in preparation for the start of a next write operation. The reset pulse output from the reset circuit 64 accordingly provides for an internal, self-timed termination of the memory write operation.
Following termination of the write operation and resetting of the addressing and accessing circuits, the write bit true line 58 and the write bit complement line 60 are both returned to logic level high. This drives the output of NAND gate 74 back to normally logic level low, which turns on p-channel pull-up transistor 82 and brings node 80 into a logic level high state. The logic level low output of NAND gate 74 is further passed through access transistor 18' to node 84, with node 84 also being driven to logic level low due to the turning on of transistor 14'. Thus nodes 80 and 84 are now returned to their normal high and low logic levels, respectively, in preparation for next operation to write data into the memory cell 10. A logic level low output from the NAND gate 74 is thus applied to the gate of upper stacked p-channel transistor 86, and a logic level low output from node 84 is applied to the gate of the lower stacked transistor 88. This dual logic level low signal application turns on transistor 86 and turns off transistor 88 producing a logic level high output at node 90 which is passed through the delay circuit 72 to return the reset signal 66 to a logic level low state (ending generation of the reset pulse).
When the write data is output from the write driver 52 to the memory, it passes through transistors 54 and 56 before presentation to the bit lines 20 and 22, respectively. At the same time, the write data is presented to NAND gate 74 and to cross-coupled transistors 76 and 78 which are designed to simulate the timing required for the write data to be presented to the memory cell 10 in the memory itself so that node 84 of the dummy memory cell 10' and node 32 of the memory cell 10 are presented with the data at substantially the same time. Since the structural and operational characteristics of the access transistors and the cross coupled transistors of the memory cell 10 and the dummy memory cell 10' (of the reset circuit 64) are identical to each other, the time required to change the state of the transistor in the memory cell 10 (i.e., effectuate a write) is substantially identical to the time required to change the state of the data in the dummy memory cell 10'. Thus, the generation of the write complete signal (i.e., node 90 going to a high logic level) by the reset circuit 64 following a change of data state at dummy memory cell 10' node 84 substantially corresponds with completion of the write operation in the memory cell 10. The resulting reset signal 66 is thus correctly timed to cause write termination after a sufficient amount of time to ensure that the write operation in the memory cell 10 is completed but also as quickly and efficiently as possible so as to promptly reset the memory for a next write operation.
It is imperative to accurate operation of the reset circuit 64 that the write data output from the write driver 52 be simultaneously presented to both the memory 10 and to the reset circuit 64. However, in certain memory design implementations elements are added to the memory design between the write driver 52 and the memory cell 10 which may alter timing and skew simultaneous write data presentation to the memory cell 10 and reset circuit 94. For example, a selectively blowable polysilicon fuse 96 may be fabricated and positioned between the pass transistor 54 and 56 the memory cell 10 along the bit lines 20 and 22, respectively. As is well known in the art, these fuses 96 are selectively blown in instances where it becomes necessary (perhaps due to an inherent defect) to disconnect a column and permanently isolate the memory cell 10 from the write bit lines 58 and 60. A drawback of the use of these fuses is that during a write operation the write driver 52 must drive the bit lines 20 and 22 through the fuses 96. As these fuses 96 can exhibit a resistance of approximately 300-1000 ohms, and the bit lines 20 and 22 exhibit a relatively high capacitance, the resulting RC circuit (with its inherent time constant .tau.) can introduce a significant delay time in the action for driving the bit lines and completing the write operation in the memory cell 10. Absent some ability to compensate for this memory cell introduced delay time, there is a risk that the write data output from the write driver 52 will not be simultaneously presented to both the memory 10 and to the reset circuit 94. If this occurs, the reset circuit 64 may generate the reset signal 66 before the write operation is completed thus jeopardizing the efficacy of the write operation and the accuracy of the data stored in the memory cell 10.
There is accordingly a need to account for circuit element introduced delays within the memory and ensure substantially simultaneous presentation of the write data output from the write driver 52 to both the memory 10 and to the reset circuit 94.